Method and device for synchronisation of data transmission between tow circuits

ABSTRACT

For synchronising the data transmission between a CMOS circuit ( 1 ) and a bipolar circuit ( 2 ) a DLL (delayed lock loop) is provided which sets a phase deviation between the operating clocks (CLK 1 , CLK 2 ) of the two circuits ( 1, 2 ), and changes the phase of at least one of the two clocks (CLK 1 , CLK 2 ) according to this phase deviation, until said the two clocks are in phase, in such a way that the data (DATA 1 ) provided by the first circuit ( 1 ) can then be taken on by the second circuit ( 2 ). To this end, the DLL circuit comprises a phase detector ( 6 ), a loop filter ( 7 ) and an adjustable element ( 8 ).

[0001] The present invention relates to a method and a correspondingdevice for synchronising the data transmission between two circuits,which in particular are designed according to different circuitengineering principles, for example CMOS and bipolar circuitengineering.

[0002] The interconnection of CMOS (Complementary Metal OxideSemiconductor) modules and bipolar modules poses major problems, forexample in high frequency circuits, since in CMOS circuits, inter alia,the operating time tolerances, due to variations in temperature andsupply voltage, are significantly greater than in bipolar circuits.Without the use of a balancing interface, therefore, the synchronisationof data and clock between the different circuits would be lost. Theabovementioned problem is conventionally solved by so-calledelastic-store interfaces, a corresponding example of which is shown inFIG. 2.

[0003]FIG. 2 shows a CMOS module 1, that writes n-bit-data DATA1 withits CMOS-clock CLK1 in a buffer memory 10, and a bipolar module 2 laterreads out or collects the buffered data in the buffer memory 10 with itsbipolar clock CLK2 in the form of n-Bit-data DATA2, in order to be ableto process this further. At no point in time should a write and a readaccess be taking place at the same memory cell of the buffer memory 10,since otherwise during a read process the bit stored in the immediatelypreceding write cycle could be overwritten by the new write cycle.Therefore in the example shown in FIG. 2 offset read and write addresscounters 11 or 13 are used, so that the undesired overwriting of thememory cells of the buffer memory 10 described above can be reliablyavoided. The write addresses generated by the write address counter 11are stored via a decoder 12 at the individual memory cells of the buffermemory 10, while the read address counter 13 for reading out of thebuffered data drives a multiplexer 14. The memory depth of the buffermemory 10, i.e. the number of memory cells present, is essentiallydependent upon the CMOS tolerances, and the buffer memory 10 can, forexample, have a memory depth of 6 (as in the example shown in FIG. 2), 8or 12.

[0004] When such an elastic store interface with circuit components10-14 is used, the associated space requirement is relatively high. Inparticular, the buffer memory 10, which works according to the FIFO(First In-First Out) principle, is relatively space-intensive and alsoincreases the power dissipation. All n information channels, usually 8or 16 bit, must be stored in a correspondingly large memory field of thebuffer memory 10 (with a bus width of 16 bits and a memory depth of 6,for example, a total of 96 flip-flops will be needed for this).

[0005] The object of the present invention is therefore to propose amethod and a corresponding device for synchronising the datatransmission between two circuits, with which the space requirement andthe power dissipation can be reduced.

[0006] This object is achieved by the method according to the inventionwith the features of claim 1 or a device with the features of claim 9.The sub-claims each define preferred and advantageous embodiments of thepresent invention.

[0007] In accordance with the invention, the phase of the first clock,with which the data is written from the first circuit to the buffermemory, and the second clock, with which the data is read out from thebuffer memory by the second circuit for further processing, isdetermined and according to this the phase of the first clock and/or thephase of the second clock is/are changed until both clocks are in phase,so that then the data buffered in the buffer memory can be taken on orread out by the second circuit without any problem. In this way,switching time tolerances of the first circuit, which may for example bedetermined by temperature or voltage changes, can be adjusted byadjustable delay elements.

[0008] The clock of the second circuit can, for example, be derived fromthe clock of the first circuit via such controllable delay elements, andthe clock from the first circuit is then, for example by performing thephase comparison, fed back to the second circuit again. The delayelements are preferably driven via a loop filter with a periodiccharacteristic curve, and the loop filter can be designed in the form ofan up/down counter. This guarantees that, for signals of the phasedetector, which compares both clocks with each other, that pointpermanently in the same direction, after a certain number of pulses anoverrun occurs and thus—as with a conventional phase locked loop—a phaseshift, so that in principle any phase deviation between the two clockscan be corrected.

[0009] The proposed interface according to the invention between the twocircuits thus comprises in principle a delay locked loop (or DLL),and—with the exception of the special design of the loop filterdescribed above—the other components of the control circuit can be builtusing known circuit components. With a design of the proposed delaystage according to the invention or of the proposed control circuitaccording to the invention using digital circuit components the counterposition of the loop filter described above can be used directly todrive the respective delay element, while otherwise a digital/analogueconverter must be provided to drive the delay element between the loopfilter and the delay element.

[0010] The present invention is in particular suitable for synchronisingthe data transmission between two circuits that have been built usingtwo different types of circuit engineering. Thus, for example, the firstcircuit can be set up in the form of a CMOS circuit and the second inthe form of a bipolar circuit. Of course, the present invention is not,however, restricted to this preferred area of application, but canbasically be applied to any circuit combination, in particular also tothe combination of two circuits set up using the same circuitengineering.

[0011] In accordance with the invention, just one clock signal needs tobe adjusted for synchronising the data transmission, so that the spacerequirement and the power dissipation can be limited.

[0012] The present invention is explained in the following withreference to the attached drawing using a preferred embodiment.

[0013]FIG. 1 shows a simplified block diagram of a device forsynchronising the data transmission between a CMOS circuit and a bipolarcircuit according to a preferred embodiment of the present invention and

[0014]FIG. 2 shows a simplified block diagram of an elastic storeinterface for synchronising the data transmission between a CMOS circuitand a bipolar circuit according to the prior art.

[0015]FIG. 1 shows a CMOS circuit 1 and a bipolar circuit 2, and then-bit data DATA1 is to be transmitted from the CMOS circuit 1 to thebipolar circuit 2. The system clock of the CMOS circuit 1 is designatedby CLK1 and the system clock of the bipolar circuit 2 by CLK2. The dataDATA1 to be transmitted are written by the CMOS circuit 1 via an outputregister 3 with the clock CLK1 in an input register 4, which functionsas a buffer memory and is present in the bipolar circuit 2. The databuffered in the input register 4 is read out by the bipolar circuit 2with the clock CLK2 via an output register 5 and made available in theform of n-bit data DATA2 for further processing. As can be seen fromFIG. 1, the clock CLK1 of the CMOS circuit 1 is derived via one or morecontrollable delay elements 8 from the clock CLK2 of the bipolar circuit2, and the clock CLK2 is made available from a clock source 9.

[0016] The operating time tolerances of the CMOS circuit 1, which can bedetermined by temperature and voltage changes, are adjusted with thehelp of the above-mentioned adjustable delay elements 8. For thispurpose, the primary system clock in the bipolar circuit is fed backagain into the bipolar circuit 2 via the CMOS circuit 1, and a phasedetector compares the original clock, i.e. the clock CLK2, and thereturning clock, i.e. the clock CLK1, with each other for their phase.The output signal from the phase detector 6, which is dependent upon thephase of the two clocks CLK1 and CLK2 or the result of the comparison,drives via a loop filter 7, the delay created by the delay element 8until both clocks CLK1 and CLK2 are in phase. The output register 5 ofthe bipolar circuit 2 can then take the data buffered in the inputregister 4 without problems and output it for further processing.

[0017] In a conventional phase control circuit, two clock signals arecontinuously compared with each other, and the control range of thephase because of the periodic repetition of the behaviour is a maximumof 360°. The phase relationships between the two clocks are repeatedeven for an infinite control range of the loop filter implemented ineach case.

[0018] The delay element 8, however, has only a limited range, which canbe used for correction of phase deviations between the two clocks CLK1and CLK2. When the circuit arrangement shown in FIG. 1 is switched on,however, the behaviour of the CMOS circuit 1 is unknown, so thataccordingly the phase delay of the CMOS circuit 1 according to therespective temperature may be large or small. In addition, the case mayarise where the phase delay of the CMOS circuit 1 has to be reduced bythe delay element 8 and, however, the delay element 8 when the circuitarrangement is switched on is already set to its lowest value, so that acorrection of the phase displacement between the two clocks CLK1 andCLK2 would be impossible.

[0019] In order to remove this problem, the loop filter 7 preferably hasa periodic characteristic curve and can be set up as a up/down counter,which is driven by a corresponding up/down counter signal of the phasedetector 6. With such a configuration of the loop filter 7, for signalsof the phase detector 6 that permanently point in the same direction,after a certain number of pulses an overrun occurs and thus a phaseshift as in a conventional phase control circuit.

[0020] The temperature- and voltage-dependent delay of the CMOS circuit1 can in some circumstances comprise a number of clock periods. To thisend, when the circuit arrangement shown in FIG. 1 is switched on aninitialisation routine is followed, with the help of which theinstantaneous delay of the CMOS circuit can be determined. In addition,the phase detector 6 compares the clocks CLK1 and CLK2 that have beenbroken down evenly with regard to their frequency by a divider factor Nand changes the delay of the delay element 8 until the phase detector 6detects a correspondence between the broken down clock CLK1 and CLK2.Here, the divider factor N is determined by the maximum expected delayand is selected as follows:

N>(maximum delay/clock period of CLK2)+1

[0021] Only when correspondence is detected, regarding the clock CLK1,CLK2 broken down by the divider factor N, by the phase detector 6 arethe original (undivided) clocks CLK1 and CLK2 applied to the phasedetector 6.

[0022] This procedure is advantageous, since in this way the delay ofthe delay element 8 following evaluation of the broken down clocks CLK1,CLK2 is set at a value, that is large enough to adjust the delay betweenthe undivided clocks CLK1, CLK2 even without phase shift.

[0023] The above description of the embodiment shown in FIG. 1 clearlyshows that unlike the conventional example shown in FIG. 2, just onesignal, namely the clock CLK1, has to be adjusted for synchronising thedata transmission between the CMOS circuit 1 and the bipolar circuit 2.With the circuit arrangement shown in FIG. 2, on the other hand, allinformation channels, normally 8- or 16-bit, must be stored in acorrespondingly large memory field of the respective buffer memory, sothat through the present invention the space requirement and the powerdissipation can be significantly reduced.

1-15 Cancelled.
 16. A method for synchronizing data transmission from atransmit circuit to a receive circuit, comprising: in response to afirst clock, the transmit circuit writing data into a buffer memory; inresponse to a second clock, the receive circuit reading the data fromthe buffer memory for further processing of the data; comparing thefirst clock and second clocks; in response to said comparing step,changing a phase relationship between the first and second clocks sothat the first and second clocks are in phase with one another duringsaid reading step, including adjusting an adjustable delay element toput the first and second clocks in phase with one another; before saidstep of comparing the first and second clocks, comparing a dividedversion of the first clock to a divided version of the second clock and,in response to said last-mentioned comparing step, adjusting theadjustable delay element to put the divided versions of the first andsecond clocks in phase with one another.
 17. The method of claim 16,including deriving the first clock from the second clock, and providingthe first clock to the receive circuit for at least one of saidcomparing steps.
 18. The method of claim 16, wherein said adjusting stepincludes using a loop filter which has a periodic characteristic curve.19. The method of claim 18, wherein said step of using a loop filterincludes driving an up/down counter with an up/down count signal. 20.The method of claim 16, including identifying a maximum delay betweenthe second clock and the first clock, defining a first value that isgreater by 1 than a ratio of the maximum delay to a period of the secondclock, selecting a divisor value that is greater than the first value,and using the divisor value to produce the divided versions of the firstand second clocks.
 21. The method of claim 16, wherein the transmitcircuit is one of a CMOS circuit and a bipolar circuit, and the receivecircuit is the other of a CMOS circuit and a bipolar circuit.
 22. Anapparatus for synchronizing data transmission from a transmit circuit toa receive circuit, comprising: a buffer memory for storing data writtenthereto by a transmit circuit operating in response to a first clock,said buffer memory further for permitting the stored data to be readtherefrom by the receive circuit operating in response to a secondclock; a phase detector for detecting a phase relationship between thefirst and second clocks; an adjustable delay element coupled to thephase detector and responsive to the phase relationship for changing thephase relationship so that the first and second clocks are in phase withone another when the data is read from the buffer memory; and the phasedetector further operable for detecting the phase relationship fordetecting a further phase relationship between a divided version of thefirst clock and a divided version of the second clock and, beforechanging the first-mentioned phase relationship, the adjustable delayelement responsive to the further phase relationship for changing thefurther phase relationship to put the divided versions of the first andsecond clocks in phase with one another.
 23. The apparatus of claim 22,wherein the adjustable delay element is further for deriving the firstclock from the second clock.
 24. The apparatus of claim 23, wherein thephase detector and the adjustable delay element are included in thereceive circuit, and wherein the phase detector includes an input forreceiving the first clock from the transmit circuit.
 25. The apparatusof claim 22, including a loop filter coupled between the adjustabledelay element and the phase detector, the adjustable delay elementdriven by the phase detector via the loop filter.
 26. The apparatus ofclaim 25, wherein the phase detector provides an output signalindicative of one of the phase relationships, wherein the loop filter isfor generating a loop filter output signal for setting a delay of theadjustable delay element, and wherein the loop filter has a periodiccharacteristic curve with regard to the phase detector output signal andthe loop filter output signal.
 27. The apparatus of claim 25, whereinthe loop filter includes an up/down counter, and the phase detectorprovides an output signal indicative of one of the phase relationships,and wherein the phase detector output signal is an up/down signal fordriving the up/down counter.
 28. The apparatus of claim 22, wherein thetransmit circuit is one of a CMOS circuit and a bipolar circuit, and thereceive circuit is the other of a CMOS circuit and a bipolar circuit.29. A device for synchronizing data transmission between first andsecond circuits comprising: a first clock signal; a second clock signal;a buffer memory into which data is written by the first circuit inaccordance with the first clock signal and out of which data is read bythe second circuit in accordance with the second clock signal; a phasedetector for comparing the phase of the first clock signal with thephase of the second clock signal; and an adjustable delay elementresponsive to the phase detector such that the phase of the first clocksignal is changed according to the comparison made by the phasedetector.
 30. The device of claim 29, wherein the first clock signal isderived from the adjustable delay element and from the second clocksignal.
 31. The device of claim 30, wherein the phase detector and theadjustable delay element are in the second circuit and the first clocksignal is in the first circuit and sent to the phase detector.
 32. Thedevice of claim 29, wherein the adjustable delay element is driven via aloop filter by the phase detector.
 33. The device of claim 32, whereinthe phase detector provides an output signal indicative of one of thephase relationships, wherein the loop filter is for generating a loopfilter output signal for setting a delay of the adjustable delayelement, and wherein the loop filter has a periodic characteristic curvewith regard to the phase detector output signal and the loop filteroutput signal.
 34. The device of claim 32, wherein the loop filterincludes an up/down counter, and the phase detector provides an outputsignal indicative of one of the phase relationships, and wherein thephase detector output signal is an up/down signal for driving theup/down counter.
 35. The device of claim 29, wherein the first circuitincludes one or a CMOS circuit and a bipolar circuit and the secondcircuit includes the other of a CMOS circuit and a bipolar circuit.